1. Field of Invention
The invention is directed to the field of non-volatile memories. More particularly, the invention relates to write commands for use with a non-volatile memory array.
2. Description of Related Art
Electronic systems typically include a processor and memory. The memory is used to store instructions and/or data. Memory can be "volatile" memory or "non-volatile." The information stored in a volatile memory is not maintained when the system is turned off. Thus, in some systems, such as that shown in the block diagram of FIG. 7, non-volatile memory is needed to guarantee that the data is continuously stored even when the system is turned off. Non-volatile memory includes mass storage devices such as disk drives as well as smaller storage devices such as ROMs. One type of ROM that is widely used is an EPROM. However, conventional EPROMS's cannot be reprogrammed once installed in an electronic system without removing the device from the system, and removal is typically not possible. Thus, many electronic designs use other devices such as EEPROMs or flash memories that can be reprogrammed in-system. Where cost is a factor, flash memories are typically chosen.
To perform various operations on a flash memory, including writing to the memory, a user must send commands to the memory. The commands indicate to the memory that a write operation (i.e., program or erase) or a multitude of other operations are to be performed. In order to assure compatibility between non-volatile memory devices, such as flash devices, and other electronic system devices, a set of standard commands have been developed. These standard commands are set out in the JEDEC Standard No. 21-C (Release 7), Configurations for Solid State Memories, .sctn. 3.5.3, incorporated herein by reference.
In order to operate, non-volatile memory devices such as flash memories require a voltage, Vcc, to be applied to at least one of the device's pins. Vcc is typically 5v, although it can be lower or higher. In addition to Vcc, which is required for read operations, many conventional devices require an additional high voltage, e.g., 12V, to be applied during a write operation that is not used during regular read operations. The requirement of such a high voltage serves to prevent accidental writing to the memory array (by the accidental sending of write commands) since this voltage will only be applied when the user desires to write to the memory device. In the interests of lowering the power consumption of flash devices and eliminating the requirement of two in-system power supplies, however, some companies have developed devices that can be written to using the same voltages as used for the read operations, e.g., Vcc=5v. Use of these "single power supply" memory devices has increased the risk of accidental overwrites of data stored in the memory.
For instance, one company that provides a single power supply memory device provides two power pins on its device. One pin is maintained at Vcc while the second pin is optionally brought to ground during read operations to prevent writes until the second power pin is raised again to Vcc. However, if the second pin is left at Vcc, there is no overwrite protection. Moreover, unless two power supply pins are provided, such protection is not even an option. Unfortunately, as with most electronic devices, pins are at a premium and the elimination of unnecessary pins is desirable. In addition, managing the control of an additional pin with such a critical single power supply function can significantly increase software complexity.
Hence, the JEDEC standard has included commands designed for single power supply memory devices so that a user cannot accidentally overwrite stored data by the accidental sending of write commands. Unfortunately, these security measures require that, for instance, every time a program operation is to be performed, a four cycle command sequence must also be performed. (For two-power-supply devices only two cycle command sequences are required). For each type of write command, program or erase, the first two cycles in the command sequence are "write unlock" cycles, indicating a write command is forthcoming and ensuring that the user indeed desires to write data to the memory cell array. The third cycle conveys the specific command for the operation, e.g., program. For a program operation, the fourth cycle in the command sequence indicates the specific address and data information to be programmed.
Each cycle is defined by a time period determined by external hardware and software. Typical write cycle times for currently available devices are approximately 200 ns-20 .mu.s, where 200 ns is generally close to the shortest cycle time that these memory devices can support. Thus, since each program command sequence requires four write cycles under the JEDEC standard, the program command sequence will require at least 800 ns. Once the command is received, actual programming will take another 10 .mu.s. Hence the program command sequence itself takes approximately 7.4% of the total programming time if a 200 ns cycle time is used. If using a 20 .mu.s cycle time, total programming time for each byte of data increases to 90 .mu.s, and the program command sequence takes 88% of total programming time. When programming over 1,000,000 bytes of data in a memory device, device programming times typically take 8-10s when using a 200 ns cycle time, but programming the same number of bytes with a 20 .mu.s cycle time results in programming times of 96-110s. Clearly the command sequence cycles can have a large effect on the perceived program time. Moreover, for many companies that program many bytes of data in large numbers of devices using, for instance, specially designed programming equipment, reducing program command sequence cycle time could greatly enhance their productivity.
Because of the potentially excessive time required to program a device using the 4-cycle-per-byte (or -per-word) method outlined by the JEDEC standard when using longer cycle times, there is a need for a method of reducing write time to non-volatile memory devices while at the same time maintaining overwrite prevention measures and reducing pin count.